1. Field of the Invention
The present invention generally relates to a power-supply-voltage reduction device and a semiconductor integrated circuit device including the device, and more particularly, to a power-supply-voltage reduction device which reduces an external power supply voltage supplied from the outside to a lower voltage suitable for circuits operable with a lower power supply voltage, and to a semiconductor integrated circuit device including the reduction device, where the reduced power supply voltage is supplied to a variety of circuits formed inside the semiconductor integrated device.
The present invention also relates to a method for fabricating an electronic device including such a power-supply-voltage reduction device, which is arranged based on an external power supply voltage.
2. Description of the Related Art
In a metal oxide semiconductor (MOS) memory such as a dynamic random-access memory (DRAM) and a static random-access memory (SRAM), a structure of an MOS transistor to be integrated has been finely structured in order to improve a density of an integrated circuit.
Along with the fine structuring of the MOS transistor, a gate-insulated film of the MOS transistor has been structured in the form of a thin film. Therefore, for mitigating an electric field applied across the gate-insulated film, and ensuring device quality, there is a need for reducing a power supply voltage.
In addition, in order to perform the fine structuring of the MOS transistor, a channel length of the MOS transistor is shortened, so that a short-channel effect appears, and the above may cause an abnormal threshold voltage in the MOS transistor. From this point, there is an additional need for reducing the power supply voltage.
Since there exist a variety of semiconductor integrated circuits which do not require a reduction of the power supply voltage surrounding the MOS transistor, it is desirable to realize a power-supply-voltage reduction device inside the MOS memory.
By realizing the power-supply-voltage reduction device inside the semiconductor integrated circuit, besides the advantages of ensuring the quality and mitigating the short-channel effect, another advantage of reducing a power consumption can be obtained, because of the power supply voltage being lower than an external power supply voltage.
And further, if the power-supply-voltage reduction circuit is constructed with a constant voltage circuit, since the power supply voltage which is supplied to internal circuits is maintained constantly regardless of changes in the external power supply voltage, there is another advantage in that a fluctuation of performance of the internal circuits due to the external supply voltage being fluctuated is removed.
FIG. 1 shows a schematic diagram of a conventional power-supply-voltage reduction device which is formed inside the DRAM. In FIG. 1, the power-supply-voltage reduction device is constructed with an enhancement-type pMOS transistor 1 for a regulator transistor, and a differential amplifier 2 controlling a gate voltage of the pMOS transistor 1.
In FIG. 1, VCC is an external power supply voltage which is supplied from the outside, Vref is a reference voltage which is generated inside the memory, and Vint is a reduced supply voltage which is supplied to given circuits in the memory.
In the power-supply-voltage reduction device, the reference voltage Vref is applied to a standard phase signal input port of the differential amplifier 2, and the reduced supply voltage Vint is applied to the reversed phase signal input port thereof, so that the reduced supply voltage Vint is controlled to be substantially maintained to the reference voltage Vref.
Recently, a DRAM system operable with the external power supply voltage of 3 to 3.3 V has been developed instead of a system operable with the voltage of 5 V.
For dealing with the new DRAM system, two methods of a power-supply-voltage construction have been implemented.
A first method is such that, in the case of the external power supply voltage VCC of 5 V, the reduced supply voltage of 3 to 3.3 V is generated through the power-supply-voltage reduction device, and in the case of the external power supply voltage VCC of 3 to 3.3 V, the external power supply is directly produced without a reduction operation of the external power supply voltage, by means of deactivating the pMOS transistor 1 by a metal option or a fuse option.
A second method is that, by setting the reference voltage Vref to less than 3 V, in the instance of not only the external power supply voltage VCC of 5 V, but also that of 3 to 3.3 V, the reduced supply voltage is generated by reducing the external power supply voltage VCC.
However, in the first method, when the external power supply voltage of 3 to 3.3 V is directly produced without the reduction operation, a supplied voltage to the internal circuits has a voltage range of 2.7 to 3.6 V for a margin of 10%. Therefore, the internal circuits are operative with such a voltage range, there is thus a problem of a fluctuation of operating speed and power consumption which depend on the power supply voltage.
On the other hand, in the second method, since the reduced supply voltage is generated by reducing the external power supply voltage VCC of 5 V or 3 to 3.3 V, the fluctuation of the operating speed and the power consumption may be suppressed. However, in this case, another problem occurs, which will be described in the following.
FIG. 2 shows a graphical representation of a static performance of the pMOS transistor 1. A horizontal axis is a source-drain voltage, and a vertical axis is a drain current. In this figure, the reduced supply voltage is set to 3.0 V. Therefore, when the external power supply voltage of 5 V or 3.3 V is supplied to a drain of the pMOS transistor 1, the source-drain voltage becomes respectively 2 V or 0.3 V. As shown in FIG. 2, in a case of the external power supply voltage of 3 to 3.3 V, the drain current for the source-drain voltage of 0.3 V is extremely degraded against that for the source-drain voltage of 2 V, so that there is a problem of degradation of the operating speed and a large fluctuation of the reduced supply voltage supplied to the internal circuits.
To produce a substantial current supply ability for a low external power supply voltage such as 3 to 3.3 V in order to solve this problem, it is required to fabricate a power-supply-voltage reduction device only suitable for the low external power supply voltage. However, since it is difficult to predict a demand for such a power-supply-voltage reduction device suitable for the low external power supply voltage, it is not efficient to fabricate a variety of reduction devices for different external power supply voltages using respective processes.